1. Field of the Invention
The present invention relates to transistor design, and, in particular, a transistor with carbon inplants used to vary the collector-to-emitter breakdown voltage. (BVCEO).
2. Background of the Invention
Electrostatic discharge (ESD) protection of radio frequency (RF) products is important as application frequencies exceed 1 GHz. Below 1 GHz application frequency, the ability to simultaneously achieve excellent ESD protection and performance objectives was possible in most CMOS, BiCMOS, and SOI applications. As semiconductor applications extend beyond 1 GHz applications from 10 to 100 GHz, providing ESD protection and satisfying performance goals will increase in difficulty. Today, high speed data rate wired, wireless, test equipment and disk drive applications are extending well above 1 GHz. Today, Silicon Germanium (SiGe) technology produces heterojunction bipolar transistors that show significant increases in unity current gain cutoff frequency (fT) every technology generation. As shown by the discussion that follows regarding the Johnson Limit, a transistor's BVCEO is a function of that transistor's unity current gain cutoff frequency.
With transistors whose unity current gain cutoff frequency fT exceed 10 GHz, the ability to provide ESD protection without impacting performance will be a significant challenge. For RF applications, ESD elements must have low capacitance, a high quality factor (Q), linearity and low noise. These criteria can not be satisfied by many of today's ESD solutions (e.g., silicon controlled rectifiers (SCR), and MOSFET transistors) leaving diode and diode configuration elements as a key choice for RF applications.
ESD Power Clamps between power rails are important for RF products because RF applications and BiCMOS chips can be small chips (e.g. low chip capacitance) and the need to scale the size of ESD structure small to reduce loading effects at the pin. Hence, using RF diode-based solutions, the current must flow through the chip power grid back to the ground plane. As a result, low impedance ESD power grids with low and/or scalable trigger solutions are needed for RF semiconductor chips. To provide an ESD solution that naturally scales with the BiCMOS technology, and utilizes the limitation of bipolar transistors, ESD power clamps were designed which take advantage of the Johnson Limit of SiGe HBT devices.
Relation Between Unitary Gain Cutoff Frequency and BVCEO:
A fundamental relationship exists between the frequency response of the transistor and maximum power applied across the transistor element known as the Johnson Limit. The Johnson Limit in its power formulation is given as(PmXc)½ƒT=Emvs/2π
where Pm is the maximum power, XC is the reactance Xc=Â½ P fT Cbc, fT is the unity current gain cutoff frequency, Em is the maximum electric field, and vs is the electron saturation velocity. In this form, the formulation states that there is an inverse relationship between the maximum power and frequency response This can also be expressed in terms of maximum voltage, Vm
 VmƒT=Emvs/2π
This formulation states that the product of the maximum velocity an electron can traverse a medium and the maximum electric field across that region is a constant. It also states that there is an inverse relationship between the transistor speed and the allowed breakdown voltage. Graphically, this is shown as follows: 
Based on the Johnson Limit condition, as BiCMOS SiGe technologies scale to provide a higher unity current gain cutoff frequency fT, the BVCEO of the transistor decreases. Hence from the Johnson Limit equation,V*mƒ*T=VmƒT=Emvs/2π
where V*mf*T is associated with a first transistor and VmfT is associated with a second transistor. The ratio of breakdown voltages can be determined as                                           V            m            *                                V            m                          =                              f            T                                f            T            *                                              [        t5        ]            
Using this Johnson relationship, an ESD power clamp can be synthesized where a trigger device with the lowest breakdown voltage can be created by using the highest cutoff frequency (fT) transistor and a clamp device with the highest breakdown device will have the lowest cutoff frequency (fT).
However, it is possible to further lower the breakdown voltage of the trigger transistor by introducing carbon into the structure of the transistor.